Basic 2-Or-Not.vhd
Date: 2015-10-07; view: 382.
Basic 2-And.vhd
BEGIN
COMPONENT nFET
COMPONENT pFET
ARCHITECTURE basic_andNot2_arch OF basic_andNot2 IS
ENTITY basic_andNot2 IS
PORT(in_1,in_2: IN STD_LOGIC;
vdd,vss: IN STD_LOGIC;
out12: OUT STD_LOGIC);
END basic_andNot2;
SIGNAL interS1: STD_LOGIC;
PORT (gate,source: IN std_logic; drain: OUT std_logic);
END COMPONENT;
PORT (gate,source: IN std_logic; drain: OUT std_logic);
END COMPONENT;
U1: pFET PORT MAP(in_1,vdd,out12);
U2: pFET PORT MAP(in_2,vdd,out12);
U3: nFET PORT MAP(in_1,interS1,out12);
U4: nFET PORT MAP(in_2,vss,interS1);
END basic_andNot2_arch;
LIBRARY IEEE;USE IEEE.std_logic_1164.ALL; ENTITY basic_and2 IS PORT(in_1,in_2: IN STD_LOGIC; vdd,vss: IN STD_LOGIC; out12: OUT STD_LOGIC);END basic_and2; ARCHITECTURE basic_and2_arch OF basic_and2 IS SIGNAL interS1: STD_LOGIC; COMPONENT basic_andNot2 PORT(in_1,in_2,vdd,vss: IN STD_LOGIC; out12: OUT STD_LOGIC); END COMPONENT; COMPONENT inverter PORT(in_inv,vdd,vss: IN STD_LOGIC; out_inv: OUT STD_LOGIC); END COMPONENT; BEGINU1: basic_andNot2 PORT MAP (in_1,in_2,vdd,vss,interS1);U2: inverter PORT MAP(interS1,vdd,vss,out12); END basic_and2_arch;LIBRARY IEEE;USE IEEE.std_logic_1164.ALL; ENTITY basic_orNot2 IS PORT(in_1,in_2: IN STD_LOGIC; vdd,vss: IN STD_LOGIC; out12: OUT STD_LOGIC);END basic_orNot2; ARCHITECTURE basic_orNot2_arch OF basic_orNot2 IS SIGNAL interS1: STD_LOGIC; COMPONENT pFET PORT (gate,source: IN std_logic; drain: OUT std_logic); END COMPONENT; COMPONENT nFET PORT (gate,source: IN std_logic; drain: OUT std_logic); END COMPONENT; BEGINU1: pFET PORT MAP(in_1,vdd,interS1);U2: pFET PORT MAP(in_2,interS1,out12);U3: nFET PORT MAP(in_1,vss,out12);U4: nFET PORT MAP(in_2,vss,out12); END basic_orNot2_arch;
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