Basic 3-Or-Not.vhd
Date: 2015-10-07; view: 457.
Basic 3-And-Not.vhd
Basic 2-Or.vhd
LIBRARY IEEE;USE IEEE.std_logic_1164.ALL; ENTITY basic_or2 IS PORT(in_1,in_2: IN STD_LOGIC; vdd,vss: IN STD_LOGIC; out12: OUT STD_LOGIC);END basic_or2; ARCHITECTURE basic_or2_arch OF basic_or2 IS SIGNAL interS1: STD_LOGIC; COMPONENT basic_orNot2 PORT(in_1,in_2,vdd,vss: IN STD_LOGIC; out12: OUT STD_LOGIC); END COMPONENT; COMPONENT inverter PORT(in_inv,vdd,vss: IN STD_LOGIC; out_inv: OUT STD_LOGIC); END COMPONENT; BEGINU1: basic_orNot2 PORT MAP (in_1,in_2,vdd,vss,interS1);U2: inverter PORT MAP(interS1,vdd,vss,out12); END basic_or2_arch;LIBRARY IEEE;USE IEEE.std_logic_1164.ALL; ENTITY basic_andNot3 IS PORT(in_1,in_2,in_3: IN STD_LOGIC; vdd,vss: IN STD_LOGIC; out12: OUT STD_LOGIC);END basic_andNot3; ARCHITECTURE basic_andNot3_arch OF basic_andNot3 IS SIGNAL interS1,interS2: STD_LOGIC; COMPONENT pFET PORT (gate,source: IN std_logic; drain: OUT std_logic); END COMPONENT; COMPONENT nFET PORT (gate,source: IN std_logic; drain: OUT std_logic); END COMPONENT; BEGINU1: pFET PORT MAP(in_1,vdd,out12);U2: pFET PORT MAP(in_2,vdd,out12);U3: pFET PORT MAP(in_3,vdd,out12); U4: nFET PORT MAP(in_1,interS2,out12);U5: nFET PORT MAP(in_2,interS1,interS2);U6: nFET PORT MAP(in_3,vss,interS1); END basic_andNot3_arch;LIBRARY IEEE;USE IEEE.std_logic_1164.ALL; ENTITY basic_orNot3 IS PORT(in_1,in_2,in_3: IN STD_LOGIC; vdd,vss: IN STD_LOGIC; out12: OUT STD_LOGIC);END basic_orNot3; ARCHITECTURE basic_orNot3_arch OF basic_orNot3 IS SIGNAL interS1,interS2: STD_LOGIC; COMPONENT pFET PORT (gate,source: IN std_logic; drain: OUT std_logic); END COMPONENT; COMPONENT nFET PORT (gate,source: IN std_logic; drain: OUT std_logic); END COMPONENT; BEGINU1: pFET PORT MAP(in_1,vdd,interS1);U2: pFET PORT MAP(in_2,interS1,interS2);U3: pFET PORT MAP(in_3,interS2,out12); U4: nFET PORT MAP(in_1,vss,out12);U5: nFET PORT MAP(in_2,vss,out12);U6: nFET PORT MAP(in_3,vss,out12); END basic_orNot3_arch;
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